1. Field of the Invention
The present invention generally relates to a method for reducing a thickness variation of a remaining nitride layer in a shallow trench isolation (STI) CMP process, and more specifically, to a method for reducing a thickness variation of a remaining nitride layer in an STI CMP process by inserting one or more predetermined active region patterns in a scribe lane for adjusting active region pattern density in a wafer.
2. Description of the Related Art
One method for forming a device isolation film of a semiconductor device is depicted in FIG. 1. As shown, a pad oxide layer 20 and a pad nitride layer 30 are formed over a semiconductor substrate 10. The pad nitride layer 30, the pad oxide layer 20, and a predetermined thickness of the semiconductor substrate 10 where a device isolation film is to be formed are etched to form a trench (not shown).
Next, an oxide film 40 (for a device isolation film) is deposited to fill the trench. The oxide film 40 deposited in the trench is then polished via a CMP process to expose the pad nitride layer 30.
In the CMP process, a High Selectivity Slurry (“HSS”) is used. As shown in FIG. 2, the thickness (tN) of a remaining pad nitride layer 30 varies depending on the positions Specifically, FIG. 2 depicts five different positions C, C1, C2, C3 and C4 in a die. FIG. 3 is a graph illustrating the thickness of the remaining pad nitride layer 30 after the STI CMP process according to the position in the die. As shown in FIGS. 2 and 3, the thickness of the remaining pad nitride layer 30 (Rnit) varies according to the position in the die as indicated in FIG. 2. This variation is due, in part, to variation in the density of active region in C, C1, C2, C3, C4, and their adjacent regions.
As illustrated in FIG. 4, when the thickness of a remaining pad nitride layer 30 in the die varies, the depths of moat 50 generated in a cleaning process for the pad nitride layer 30 varies according to the position in the die. This phenomenon increases a cell threshold voltage and decreases a process margin, thereby resulting in a deterioration of device characteristics.